好吧，算我输给你了，你赢了
呵呵，恭喜
那么，愿意来nvidia吗？
我们这里有很多的空缺，包括美国总部的职位我都可以帮你推荐的
也许这职位比较适合你哦
RESPONSIBILITIES:
- Design and develop state of the art 3D graphics hardware architecture. Working within a team of graphics architects and ASIC engineers to document, design, develop and verify functional and performance models for NVIDIA’s new chips.
- Develop tests, testplans, and testing infrastructure to validate the performance and functional correctness of ASICs modeled in C++, RTL and real silicon.
- Develop tests and tools to collect useful information for 3D graphics performance analysis.
- Analyze 3D graphics driver and hardware performance to determine underlying causes for the performance shortcomings. The work is done based on industrial standard benchmarks, popular games and applications.
REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Well understanding the theory and process of 3D graphics pipeline, a strong plus to understand state of art GPU architectures - Familiar with 3D graphics APIs, d3d or/and OpenGL - Minimum 2 years experience in one of the areas: GPU architecture design & development 3D graphics drivers (d3d or OpenGL) development 3D games or 3D applications development
- Experience of performance analysis, especially for software or hardware 3D graphics products - Strong Computer Science background especially in the area of computer system programming
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus. - Well organized problem solving capability and communication skills - Excellent English writing for engineering documentation, English oral well enough to attend meetings 4. GPU ASIC Physical Design Engineer
RESPONSIBILITIES: - Synthesis at full chip level. -
Formal Verification at full chip level. -
Early stage Floorplanning and clock distribution.
- Static Timing Analysis (STA) at both the block and full chip level using industry standard STA tools - Work in conjunction with Place and Route Engineers to achieve timing closure
- Develop custom timing scripts using tcl/perl for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop tcl and dc-shell scripts for performing ECO's.
- Contribute to the ongoing development and enhancement of our entire timing methodology - Verify all DFT logics with simulation - Verify miscellaneous design in the chip, such as clock and pads.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science - Familiar with ASIC design and methodologies - Understanding & hands on experience with industry standard synthesis, formal verification and STA tools,
hands-on experience on running DFT related tests is a plus
- Strong RTL programming ability, C/C++ preferred - Proficient in programming/scripting languages : Perl, tcl, make, Linux/Unix shell script. - Strong interest in ASIC design/verification - Excellent written and verbal communication skills - Ability to multiplex many issues, set priorities, and work in a team environment - Keep up to date with leading edge technologies
[ 本帖最后由 找公道 于 2008-2-15 17:54 编辑 ] | 
楼主: aluzi
京公网安备 11010602010207号
( 京ICP证041102号，京ICP备09075138号-9 )
狗仔卡
发表于 2008-2-14 23:10
